1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to improvements in ground resistance and operation characteristics of a nonvolatile erasable programmable read-only memory device (hereinafter referred to as EPROM).
2. Description of the Prior Art
FIG. 1 is a block diagram showing a construction of a conventional UV-EPROM (Ultraviolet EPROM).
Referring to the figure, an X address decoder 2 and a Y gate sense amplifier 3 for selecting rows and columns of memory cells are connected to a memory matrix 1 comprising a plurality of memory transistors (to be described later) arranged in rows and columns. A Y address decoder 4 which supplies column selection information is connected to the Y gate sense amplifier 3, and the X address decoder 2 and the Y address decoder 4 are respectively connected to an address buffer 5 in which address information is temporarily stored. An input/output buffer 7 which temporarily stores input/output data is connected to the Y gate sense amplifier 3. The address buffer 5 and the input/output buffer 7 are connected to a control logic 6 which controls operation of the EPROM. The control logic 6 performs control based on a chip enable signal CE, an output enable signal OE and a program signal PGM.
FIG. 2 is a circuit diagram showing in perspective a schematic construction of the memory cell matrix 1 shown in FIG. 1.
In the figure, a plurality of word lines WL1, WL2 to WLi are arranged in the row direction and a plurality of bit lines BL1, BL2 to BLi are arranged in the column direction so as to intersect the word lines orthogonally, thereby forming a matrix. Memory transistors Q11, Q12 to Qii each having a floating gate are arranged at respective intersections of the word lines and the bit lines. Each memory transistor has its drain connected to the corresponding bit line, its control gate connected to the corresponding word line and its source connected to the corresponding one of ground lines (S1, S2 etc.). As is shown in the figure, the sources of the memory transistors belonging to the same row are connected to each other and to the ground lines (S1, S2 etc.) arranged on both sides with connection resistances R being individually generated.
FIG. 3 is a plan view showing a portion of a definite structure of a conventional memory cell matrix and FIGS. 4 and 5 are cross sectional views taken along the lines IV--IV and V--V of FIG. 3, respectively.
Referring to FIGS. 3 to 5, the structure of the memory cell matrix will be described. An N.sup.+ impurity region 26 which will be the drain region of a memory transistor and an N.sup.+ impurity region 28 which will be the source region thereof are formed on a main surface of a semiconductor substrate 18. A floating gate 14 is formed on a channel region which is sandwiched by the N.sup.+ impurity regions 26 and 28 with a first gate oxide film 20 interposed therebetween. The first gate oxide film 20 is sandwiched by a thick isolating oxide film 19 formed on the main surface of the semiconductor substrate 18 whereby the active region thereof is ensured. A control gate 15a formed of polyside is formed on the floating gate 14 with a second gate oxide film 22 interposed therebetween, and the control gates 15a of the respective transistors are tied to each other in the row direction to form a word line 15. An interlayer insulating film 24 is formed on the entire main surface of the semiconductor substrate 1 to cover the word line 15. The interlayer insulating film 24 has contact holes 12 to provide contact with each impurity region 26. Bit lines 16 of aluminum are formed in the column direction on the entire insulating film 24 including the contact holes. The impurity regions 28 as the source regions are connected to each other to extend in the row direction and are connected to the source lines 17 extending in the column direction through the contact holes 13. Although not shown in the figure, normally one source line 17 (denoted by S1, S2 etc.) is provided for every sixteen bit lines 16.
Writing operation into the memory transistors in the EPROM thus constructed will be briefly described referring to FIGS. 1 to 6.
Address signals A0 to Ai which will be X address signals (word line selecting signals) and Y address signals (bit line selecting signals) are in parallel inputted to the address buffer 5 and those signals are applied to the Y gate sense amplifier 3 through the X address decoder 2 and the Y address decoder 4, respectively. Consequently, one word line and one bit line are selected and a high voltage Vpp (about 12.5 V for the integration scale of 1M bit) is applied thereto. On this occasion, the non-selected word lines WL and all the source lines are brought to the ground level and the non-selected bit lines BL are brought into the floating state.
Consequently, the high voltage Vpp is applied to the drain region 26 and the control gate 15a of the memory transistor to which the selected word line and bit line are connected, and, since the potential of the source region 28 is at the ground level, a relatively large current flows to the channel of the transistor. Therefore, hot electrons are injected into the first gate oxide film 20 near the drain region 26 and into the floating gate 14 due to the electric field in this oxide film 20. As a result, electrons are stored in the floating gate 14, causing increase of the threshold voltage of the transistor. In other words, the writing operation is carried out. The electrons stored in the floating gate 14 are maintained even after the application of the high voltage Vpp since the floating gate 14 and its surrounding regions are covered with the insulating film.
On the other hand, erasing operation is performed in a manner in which energy is applied to the electrons stored in the floating gate 14 by application of ultraviolet rays to cause the electrons to return to the control gate 15a or the semiconductor substrate 18.
FIG. 6 is a graph showing current/voltage characteristics of a memory transistor in an erased state and a written state.
The written or erased state is set dependent on presence or absence of the electrons in the floating gate 14 of the transistor. As is shown in the figure, the threshold voltage of the memory transistor in the written state (where "0" is stored) is different from that in the erased state (where "1" is stored). Therefore, nonvolatile information can be obtained by setting the intermediate value as a reading gate voltage V.sub.R. More specifically, at the reading gate voltage V.sub.R shown in the figure, the memory transistor becomes nonconductive in the written state, so that no current flows to the bit line. On the other hand, the memory transistor becomes conductive in the erased state, so that current flows to the bit line.
Next, reading operation of the memory transistor of the EPROM will be briefly described with reference to FIGS. 1 to 5.
In the same manner as in the above described writing operation, address signals A0 to Ai which will be the X address signals and the Y address signals are in parallel inputted to the address buffer 5 and one word line and one bit line are selected. Let us consider a case in which a word line WL2 and a bit line BL2 are selected, for example. In this case, the presence or absence of information in the memory transistor Q22 is read. A voltage V.sub.R is applied to the word line WL2 while a prescribed voltage is applied to the bit line BL2. Other non-selected word lines and all the source lines are brought to the ground level and other non-selected bit lines are brought into the floating state. Consequently, a prescribed voltage is applied to the drain region of the transistor Q22, and, since the source region is at the ground potential, the drain current as shown in FIG. 7 flows between the source and drain regions if the transistor Q22 is in the erased state. This means that electric current flows in the bit line BL2. On the other hand, if the transistor Q22 is in the written state, electric current hardly flows between the source and drain regions, that is, in the bit line BL2. The current flow in the selected bit line BL2 brings about a change in voltage applied to the bit line BL2, and this change based on a reference voltage is detected and amplified by the Y gate sense amplifier 3. The detected and amplified voltage signal is obtained through the input/output buffer 7 as information and thus the reading operation is carried out.
In the conventional UV-EPROM, it is necessary to set the source potential of the memory transistor to the ground level for writing and reading as described above. Consequently, the source region 28 of each memory transistor is connected to the source line 17 through the contact hole 13 by means of an impurity region 11, as shown in FIGS. 2 and 3, so as to be set to the ground level.
However, the source potential of the memory transistor exhibits a voltage value slightly higher than the ground level due to voltage drop through resistance components of the impurity region 11.
FIG. 7 shows an equivalent circuit of one memory transistor.
In the figure, the impurity region 11 has resistance component R1 and R2. The resistance component R1 is a resistance component from the source line SL.sub.L on the left of the memory transistor to the source region (that is, the sum of a predetermined number of connection resistances in FIG. 2) and the resistance component R2 is a resistance component from the source line SL.sub.R on the right of the memory transistor to the source region (that is, the sum of a predetermined number of connection resistances in FIG. 2).
Now, let us calculate the resistance values of the resistance components R1 and R2. If the devices are highly integrated for increase of the capacity in the actual process technology, at least 80 .OMEGA./.quadrature. needs to be considered as a sheet resistance value of the impurity region 11. Accordingly, the impurity region 11 has about 3.quadrature. for each bit line BL and 0.5.quadrature. to the center of the contact hole of the source line SL. For example, in a typical construction including 16 bit lines BL between the source lines SL.sub.L and SL.sub.R, let us assume a case in which the memory transistor is connected to the eighth bit line BL from the left source line SL.sub.L (that is, the ninth bit line BL from the right source line SL.sub.R). The resistance components R1 and R2 in this case are as follows. ##EQU1##
Thus, the composite resistance RS.sub.8 of those resistance components is about 1 K.OMEGA..
Consequently, since a current value in writing operation is about 0.5 mA at the maximum, the source potential of the memory transistor is unavoidably increased to about 0.5 V at the maximum. Considering that a permissible error range of the high voltage Vpp is normally about .+-.0.3 V, the characteristics for writing operation are apparently deteriorated, which might cause erroneous operation. Particularly, in the case of the UV-EPROM of a large capacity, a width of a source line is decreased because of its large integration scale. As a result, the sheet resistance value tends to be increased, which further aggravates the above described problem. In addition, the characteristics for reading operation are also deteriorated for the same reasons.
The resistance components R1.sub.1 and R2.sub.1 of a memory transistor connected with the first bit line BL from the left source line SL.sub.L (that is, the 16th bit line BL from the right source line SL.sub.R) are as follows. ##EQU2## Thus, the composite resistance RS thereof is about 260 .OMEGA.. This value is considerably different from the value (1 K.OMEGA.) of the composite resistance RS.sub.8 connected to the eighth bit line BL from the source line SL.sub.L. This means that the source potential of the memory transistor differs dependent on the bit line BL connected thereto. As a result, the characteristics for writing operation and those for reading operation vary due to the difference of the bit lines connected thereto and memory transistors having uniform electric characteristics cannot be formed.